I’m a Staff HBM Design Engineer at Micron Technology, focused on advancing high-bandwidth memory through high-speed, power-efficient circuit design.
I focus on JEDEC HBM PHY DWORD design and I/O integration to optimize speed and power efficiency. My responsibilities include overseeing layout, floorplanning, placement, and routing, as well as supporting pre-silicon verification and post-silicon validation.
I collaborate with different engineering teams to close timing, power, and reliability requirements. I also support silicon debug through voltage-frequency (V/F) shmoo analysis, margin characterization, and signal and power integrity (SI/PI) investigations.
I graduated from Georgia Institute of Technology with an MSECE, after earning my bachelor’s degree in electrical engineering at Virginia Tech.
I’m motivated by the opportunity to advance semiconductor design and collaborate with cross-disciplinary teams to achieve cutting-edge innovation.