Posts

1-Bit SRAM Cell in 45-nm CMOS Technology with Integrated Dynamic Power Supply
Dynamic Cell Vcc proves the improvement in both Read and Write margins and leakage saving
Zhe Liu, Dylan Nektalov
Last updated on Feb 12, 2022 8 min read SRAM, Validation
A 12-bit Two-Stage Pipelined SAR ADC design
This page presents a two stage fully differential pipelined SAR ADC design that I worked on during Spring 2021
Zhe Liu, Shida Zhang
Last updated on Dec 13, 2021 4 min read ADC
A 12-bit Two-Stage Pipelined SAR ADC design
FetoMic
A Phonocardiography Approach to Low-Cost Fetal Heart Monitoring
Zhe Liu
Dec 13, 2020 1 min read FetoMic