1-Bit SRAM Cell in 45-nm CMOS Technology with Integrated Dynamic Power Supply

Mon, 10 Jan 2022 00:00:00 +0000

Overview

The design exhibits a 4 GHz 1-bit SRAM cell on 45nm CMOS technology. A based dynamic power supply is integrated into the design with a motivation to switch between two voltage levels (Vcc_hi and Vcc_lo) during READ and WRITE operations. This design has been implemented in Cadence Virtuoso for both schematic as well as the layout. The simulation result has proven the improvement in both Read and Write margins. Furthermore, simulation showed the SRAM cell leakage power consumption is reduced.

PROBLEM CONTEXT

One of the main focuses of small-scale SRAM design is to achieve a balanced cell stability with optimized device sizing. However, there are a few challenges that need to be faced. One of these challenges is growing threshold voltage variations due to random dopant fluctuations. This can raise the sensitivity of status noise margin (SNM) to these process variations. Additionally, a mismatch in threshold voltage can lead to a mismatch in current on both halves of an SRAM cell. Generally, we want to prevent degradation of SNM, and we want the current on both halves to be identical. But we cannot dynamically change the threshold voltage of the sizing of these transistors. Power dissipation in SRAM circuits can be categorized into two main types - dynamic and static power dissipation. For static power dissipation, it is due to leakage current drawn from the power line. The main contributor of leakage current is the sub-threshold current. For SRAM, during idle phase, the workline (WL) is at WL=0 and two bitlines are precharged to BL=1, BLB=1. Thus there are two major leakage paths, 1) Cell Vcc to ground and 2) BL (BLB) to ground through the access transistor. Generally, the static power dissipation can be expressed as equation: Pstatict =VddIsube(Vgs -Vt)/nVth We can see the exponential increase of subthreshold leakage drain current with decreasing Vt for a given Vgs. This further proves that changing threshold voltage may lead to more negative impact on SRAM operation. In section II, we will discuss our proposed design and what this contributes to cell margins, stability, and leakage.

STATE OF THE ART & CONTRIBUTION

We propose dynamically switching between two voltage levels during read and write operations. In doing so, we can improve read and write margins independently without compromising each other. During write mode, we apply a supply voltage lower than the Word Line (WL) voltage. This weakens the pull-up network of the cell. During a read operation, we apply a supply voltage larger than the WL voltage. This strengthens the pull-down network which reduces read voltage and increases the trip point. Earlier research [1] has shown how margins can be improved using a dynamic power supply voltage. But they exclude Monte Carlo methodologies to find a relationship between supply voltage and average access delay. In this paper, we plan to confirm their key discoveries in margins and leakage power saving by conducting a waveform analysis on an SRAM schematic. Then, we propose designing an SRAM cell layout and conducting a Monte Carlo simulation to model a gaussian distribution of average access time. We then estimate read and write failures based on this distribution. The goal of this design is to improve margins, reduce access delay, and increase leakage power saving.

METHODOLOGY

First, a schematic of an SRAM was created. Pfets were sized to 90 nm. Access transistors were sized to 135 nm. Nfets were sized to 180 nm. This cell was used for waveform analysis to measure the margins. To measure the write margin, The bit line (BL) voltage was sweeped to estimate the minimum voltage needed to create a transition at the storage node. To measure the read margin, we needed to find the difference between the trip point and the read voltage. We then implemented a layout for one SRAM cell because layout will help us understand the intricate details of parasites.

Layout of SRAM cell

Parasitics Capacitance of SRAM cell

Also, a Monte Carlo simulation could be done on the layout to help us study the Rise and Fall delay improvement of our proposed method. The SRAM cell layout followed a classical design approach. The cell has a length of 1.67nm and width of 1.93nm. After DRC and LVS checks, a netlist is created using PEX tools. The netlist is for the use of HSpice to help us with Monte Carlo analysis. We applied ΔVt = 0.08V with 5 nm change in Wp, Lp, and Ln, 10 nm change in Wn. For the delay analysis, the fall delay is defined as the time that data fall from 95% to 5% of Vcc. For rise delay, it is defined as the time that data rises from 5% to 95% of Vcc.

KEY FINDINGS

Using a standard 1.0V supply voltage, the write margin was measured to be 397mV. With a 800mV supply voltage, the write margin was measured to be 481mV. So, the write margin increased when we apply Vcc_Low. Two waveforms can be seen below that illustrate the waveform for this transient analysis.

Write margin for baseline

Write margin for proposed dual Vcc design

Next, the read margins were measured. The switching threshold was measured to be 415mV using a DC sweep. Then, both BLs were precharged to 1.0V. When WL high, the voltage at the storage node was measured under both scenarios - this is the read voltage. The read margin is the difference between the trip point and the read voltage. With standard supply voltage, the read margin was estimated to be 271mv. With Vcc_Hi, it was estimated to be 285mV. So the read margin was measured to be higher with Vcc_High.

Read margin for baseline

Read margin for proposed dual Vcc design

To perform the statistical analysis of the SRAM cell, a Monte Carlo simulation of 800 samples has been carried out. Fig. 3 below is the Monte Carlo simulation result for writing a “1” on Q.

Baseline Monte Carlo simulation result for writing “1”

The rise and fall delay were measured for both baseline and our proposed dual Vcc method. For fall delay, the average fall delay for our method decreased to 252.26 ps compared to average fall delay of 329.46 ps for baseline. However, the proposed dual Vcc method shows a degraded rise delay. The baseline has an average rise delay of 115.82 ps while our method has an average rise delay of 127.4 ps. This is one trade-off for using lower Vcc. In a MOSFET, the higher the difference between the gate and source voltages, the higher the current that transistor will pass. The driving voltages on the gates are reduced when Vcc is reduced, as is the amount of current they pass. Because SRAM loads are mostly capacitive, the amount of current that is delivered directly affects the rate at which that node’s voltage changes. Hence, the rise delay is larger.

Monte Carlo distribution for fall delay

Monte Carlo distribution for rise delay

A leakage analysis has been performed on one SRAM cell. The reported leakage current at t=1.59 ns for baseline 1V Vcc is 8.84 nA. As for our proposed dual Vcc operation, the standby voltage for cell supply is 0.8V. At same time stamps, the leakage current is 3.037 nA. Compare the result, our dual Vcc method saved around 72.52% of leakage power during idle phase. We then performed a parametric analysis and sweeped cell Vcc from 0.8V to 1.2V. As the result shows in the figure below. The leakage saving is maximized at Vcc = 0.8V.

Vcc vs. Leakage current in idle phase

Below is a summary of our analysis. With our proposed design, we achieved a higher read and write margin. Furthermore, we achieved a lower average fall delay, but not a faster rise time. One solution could be raising the supply voltage when the storage nodes meet to help with amplification. That way the P-FETs are stronger. All in all, we can generally improve write operations, while minimizing negative impacts in rise delay, which makes this an effective design.

Item	Write Margin	Read Margin	Monte Carlo Average Fall Delay	Monte Carlo Average Rise Delay
Baseline	397.8 mV	271 mV	329.46 ps	115.82 ps
Dynamic Vcc	481.7 mV	285 mV	252.26 ps	127.4 ps

FUTURE WORK

In the future, we plan to expand our work from one cell to one bank (2kB). Our hope would be to integrate column-based power supply techniques to further improve cell stability. That way, we can test our functionality under a more complex scheme. In addition, we could further analyze leakage power saving for a more complete design.

References

[1] K. Zhang et al., “A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply,” ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005., 2005, pp. 474-611 Vol. 1, doi: 10.1109/ISSCC.2005.1494075. [2] 6T SRAM Cell Design, https://www.iue.tuwien.ac.at/phd/entner/node34.html E. Grossar, M. Stucchi, K. Maex and W. Dehaene, “Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies,” in IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2577-2588, Nov. 2006, doi: 10.1109/JSSC.2006.883344. [3] Tripti Tripathi , Durg Singh Chauhan, Sanjay Kumar Singh, “A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability,” Journal of Low Power Electronics and Applications [4] M. Mamidipaka, K Khouri, N Dutt, M. Abadir, “Leakage Power Estimation in SRAMs,” CECS Technical Report #03-32

A 12-bit Two-Stage Pipelined SAR ADC design

Thu, 13 May 2021 00:00:00 +0000

Overview

In this project, we designed a 2-stage pipelined Successive Approximation Register (SAR) Analog to Digital Converter (ADC). SAR ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations. The pipelined SAR architecture divides a moderate resolution SAR ADC into some low resolution SAR ADCs. The target specifications are given in the following table:

Item	Specifications
Technology	45nm (NCSU FreePDK45)
Power supply	VDD = 1.2V, VSS = 0V
Resistor size	< 100kΩ
Capacitor size	2fF~ 10pF
ENOB@ Nyquist rate	>12bits
Sampling rate	>30MS/s
Walden figure-of-merit (FOM)	< 100-fJ/conversion-step

Get Started

High Level Block Diagram of the Pipelined SAR ADC

The diagram above shows the block diagram of the SAR ADC architecture. The ADC is a pipeline of a 6-bit and a 8-bit SAR ADCs. We decide to use differential sampling in order to cancel the common mode sampling offset. Furthermore, Vcm-based switching technique is used in both stages to lower the power consumption of the whole system.

Stage 1 Schematic Diagram

The first stage has 6-bit effective resolution. The first stage sub-ADC and CDAC share the same sampling capacitor array. There are several typical switching techniques that are available. We decide to use Vcm based switching technique mainly because the low power consumption and faster settling speed. However, one biggest drawback of this method is that it requires extra switches to control each capacitor. There are three possibilities at all sampling capacitors. Before the certain bit compared, the corresponding capacitor’s bottom plate is connected to Vcm. After comparison, its bottom plate will be connected to either ground or Vref depends on the comparing result is 1 or 0. Notice that the positive pair sampling capacitor array and the negative pair sampling capacitor array are connected opposite to each other. These sets of switches are controlled by a SAR logic unit which I’ll go over in next section. Additional independent clock sets are used to make sure each capacitor is in the right phase.

Stage 2 Schematic Diagram

The second stage is a 8-bit SAR ADC. The use of SAR architecture in the second stage enables a large resolution in this single stage. The implementation is very similar compare to the first stage but has two more capacitor sets.

SAR Logic

6-bit SAR Logic

The classic SAR architecture is use due to its straightforward design technique. Figure above is the implementation on Cadence. It consists of a set of ring counter and a set of shift regisiter. There are 2x6+2 = 14 D flip flops in use. For each conversion, piror to the first clock rising edge, RESET will first clocked high to reset all flip flop’s output to 0. After that, the RESET signal remains low for the reset of the process. Once the first rising edge approaches, the MSB flip flop is set to 1. Then when second rising edge approaches, the counter shifts 1 to the next flip flop until it reaches the LSB. SAR logic determains the value of bit one by one based on the comparator’s output. For a 6-bit SAR logic, it requires 1+6 = 7 cycles to complete one single conversion. Table below is the algorithm of 6-bit SAR logic.

Clock	D1	D2	D3	D4	D5	D6	COMP. Out
RESET	0	0	0	0	0	0	–
1	1	0	0	0	0	0	D1
2	D1	1	0	0	0	0	D2
3	D1	D2	1	0	0	0	D3
4	D1	D2	D3	1	0	0	D4
5	D1	D2	D3	D4	1	0	D5
6	D1	D2	D3	D4	D5	1	D6
7	D1	D2	D3	D4	D5	D6	–

Below is the SAR Logic testing result. Notice that the input (Data) is set to 110000. Our SAR Logic output for each bit matches the input correctly.

SAR logic testing

D Flip Flop

Circuit architecture for D Flip Flop

Because SAR logic uses flip flop, we decide to implement a Positive-edge-triggered D flip-flop with Clear and Preset. Here, three input NAND gates are used. Below is the truth table of our DFF.

Truth Table for D Flip Flop

Comparator

strongARM comparator

For the comparator, the StrongARM latch is selected for our design.

License

FetoMic

Sun, 13 Dec 2020 00:00:00 +0000

Posts | Zhe Liu

1-Bit SRAM Cell in 45-nm CMOS Technology with Integrated Dynamic Power Supply

Overview

PROBLEM CONTEXT

STATE OF THE ART & CONTRIBUTION

METHODOLOGY

KEY FINDINGS

FUTURE WORK

References

A 12-bit Two-Stage Pipelined SAR ADC design

Overview

Get Started

SAR Logic

D Flip Flop

Comparator

License

FetoMic

Overview